As the complexities of digital electronics and custom System on a Chip IC designs are increasing, the challenges associated with the design and verification of complex digital systems are becoming more and more profound. A higher layer of abstraction is needed in both design and verification flow to address complexities of modern solutions. We have started with schematic capture flow long time ago and evolved from Verilog/VHDL flow to high level synthesis tools, SystemVerilog and UVM.

Custom State Machines, network/packet processing, custom multiport memory controllers, data buffering and traffic management schemes are just some of the examples of the logic blocks that we have done in the past.